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1 for more information www.analog.com document feedback typical application features description en55022b compliant 58v, 4a step-down dc/dc module regulator 4a, 24v output low emi dc/dc module regulator with analog output current indicator applications n complete low emi switch mode power supply n en55022 class b compliant n wide input voltage range: 3.1v to 58v n up to 4a output current n output voltage range: 0.5v v out 0.94 ? v in n 1.67% total dc output voltage error over line, load and temperature (C40c to 125c) n parallel and current share with multiple ltm4653s n analog output current indicator n programmable input voltage limiting n constant-frequency current mode control n power good indicator and programmable soft-start n overcurrent/overvoltage/overtemperature protection n 15mm 9mm 5.01mm bga package n avionics, industrial control and test equipment n video, imaging and instrumentation n 48v telecom and network power supplies n rf systems all registered trademarks and trademarks are the property of their respective owners. protected by u.s. patents, including 5481178, 5705919, 5847554, 6580258. radiated emission scan in a 10m chamber ltm4653 delivering 24v out at 3.5a, from 48v in pins not used in this circuit: clkin, pgood, compb pgdfb, sw, extv cc temp + , temp ? , nc iseta gnd isetb v in sv in v d run intv cc vinreg compa f set v out ltm4653 24v out , up to 4a i out analog output current indicator v imon = 0.25 ? i out 10f 2 load 124k 10nf 499 481k 4.7 f 4.7 f v in 28v to 58v 4653 ta01a v osns sgnd pgnd imona imonb 0 0 0 0 0 0 0 0 0 r 0 0 0 0 0 0 0 0 0 0 000 0 r r r 0 0 the ltm ? 4653 is an ultralow noise 58v, 4a dc/dc step- down module ? regulator designed to meet the radiated emissions requirements of en55022. conducted emis - sion requirements can be met by adding standard filter components. included in the package are the switching controller , power mosfet s, inductor, filters and support components. operating over an input voltage range of 3.1v to 58v , the ltm4653 supports an output voltage range of 0.5v to 94% of v in , and a switching frequency range of 250khz to 3mhz (400khz default), each set by a single resistor. for high load currents, the ltm4653 can be paralleled in polyphase ? operation and synchronized to an external clock. only the bulk input and output filter capacitors are needed to finish the design. the ltm4653 is offered in a 15mm 9mm 5.01mm bga package with snpb or rohs compliant terminal finish. lt m4653 rev 0
2 for more information www.analog.com pin configuration absolute maximum ratings terminal voltages v in , v d , sv in , sw, v out , v osns , iseta .... C 0. 3v to 60v gn d, isetb, extv cc ............................ C 0.3 v to 28v ru n .................................... gn d C 0.3v to pgnd+ 60v in tv cc , pgdfb, vinreg, compa, compb, imona, imonb ........................................ C 0. 3v to 4v f set ................................................... C 0.3 v to intv cc clkin, pgood (relative to gnd) ........... C 0. 3v to 6v terminal currents in tv cc peak output current (note 8) ................ 30m a t emp + .................................................. C 1ma to 10ma t emp C ................................................. C 10m a to 1ma temperatures in ternal operating temperature range (note 2) ............................................. C 40 c to 125 c st orage temperature range .............. C 55 c to 125 c pe ak solder reflow package body temperature ............................................ 245 c (note 1) (all voltages relative to v out C unless otherwise indicated) 0 r r t jmax = 125c jctop = 20.6c/w, jcbottom = 5.1c/w, jb = 6.0c/w, ja = 15.5c/w values determined per jesd51-12 weight = 1.8 grams order information part number pad or ball finish part marking* package type msl rating temperature range (see note 2) device finish code ltm4653ey#pbf sac305 (rohs) ltm4653y e1 bga 3 C40c to 125c ltm4653iy#pbf sac305 (rohs) e1 C40c to 125c ltm4653iy snpb (63/37) e0 C40c to 125c ? device temperature grade is indicated by a label on the shipping container. ? pad or ball finish code is per ipc/jedec j-std-609. ? terminal finish part marking: www.linear.com/leadfree ? this product is not recommended for second side reflow. for more information, go to www.linear.com/bga-assy ? recommended bga pcb assembly and manufacturing procedures: www .linear.com/bga-assy ? bga package and tray drawings: www.linear.com/packaging ? this product is moisture sensitive. for more information, go to: www .linear.com/bga-assy http://www.linear.com/product/ltm4653#orderinfo lt m4653 rev 0
3 for more information www.analog.com the l denotes the specifications which apply over the specified internal operating temperature range (note 2). t a = 25c, test circuit, v in = sv in = 48v, extv cc = 24v, run = 3.3v, r iset = 480k, r fset = 57.6k, f sw = 1.5mhz (clkin driven with 1.2mhz clock signal) unless otherwise noted. symbol parameter conditions min typ max units sv in(dc) , v in(dc) input dc voltage l 3.1 58 v v out(range) range of output voltage regulation 0.5v iseta - sgnd 0.94v in , i out = 0a (see note 6) l 0.5 0.94v in v v out(24vdc) output voltage total variation with line and load at v out = 24v 28v v in 58v, 0a i out 4a, c inh = 4.7f, c d = 4.7f, c outh = 2 47f, clkin driven with 1.5mhz clock l 23.6 24 24.4 v v out(0.5vdc) output voltage total variation with line and load at v out = 0.5v measuring v osns - iseta 3.1v v in 13.2v, 0a i out 4a, c inh = 4.7f, c d = 4.7f, c outh = 2 47f, iseta = 500mv, r fset = n/u (note 5) l C15 0 15 mv input specifications v in(uvlo) sv in undervoltage lockout threshold sv in rising sv in falling hysteresis l l l 2.4 150 2.85 2.6 250 3.1 2.9 v v mv v in(ovlo) sv in overvoltage lockout rising (note 4) 64 68 v v in(hys) sv in overvoltage lockout hysteresis (note 4) 2 4 v i inrush(vin) input inrush current at start-up c inh = 4.7f, c d = 4.7f, c outh = 2 47f; i out = 0a, iseta electrically connected to isetb 300 ma i q(svin) input supply bias current shutdown, run = gnd run = v in 16 450 30 a a i s(vin, fcm) input supply current clkin open circuit, i out = 4a 2.1 a i s(vin, shutdown) input supply current in shutdown shutdown, run = gnd 4 a output specifications i out v out output continuous current range (note 3) 0 4 a ?v out(line) /v out line regulation accuracy i out = 0a, 28v v in 58v l 0.05 0.1 % ?v out(load) /v out load regulation accuracy v in = 48v, 0a i out 4a l 0.05 0.75 % v out(ac) output voltage ripple, v out v in = 12v, iseta = 5v 2 mv pCp f s v out ripple frequency iseta = 5v, r fset = 57.6k, clkin open circuit l 1.7 1.95 2.2 mhz ?v out(start) turn-on overshoot 8 mv t start turn-on start-up time delay measured from v in toggling from 0v to 48v to pgood exceeding 3v; pgood having a 100k pull-up to 3.3v, vpgfb resistor-divider network as shown in test circuit, r iseta = 480k, iseta electrically connected to isetb and clkin driven with 1.5mhz clock l 4 9 ms ?v out(ls) peak output voltage deviation for dynamic load step i out : 0a to 2a and 2a to 0a load steps in 1s, c outh ?= 47f 2 400 mv t settle settling time for dynamic load step i out : 0a to 2a and 2a to 0a load steps in 1s, c outh = 47f 2 50 s i out(ocl) i out C output current limit 5.5 a control section i iseta reference current of iseta pin v iseta = 0.5v, 3.1v v in 13.2v v iseta = 24v, 28v v in 58v l l 49.3 49 50 50 50.7 51 a a i vosns v osns leakage current v in = sv in = run = iseta = 58v 600 a t on(min) minimum on-time (note 4 ) 60 ns electrical characteristics lt m4653 rev 0
4 for more information www.analog.com the l denotes the specifications which apply over the specified internal operating temperature range (note 2). t a = 25c, test circuit, v in = sv in = 48v, extv cc = 24v, run = 3.3v, r iset = 480k, r fset = 57.6k, f sw = 1.5mhz (clkin driven with 1.2mhz clock signal) unless otherwise noted. symbol parameter conditions min typ max units v run run turn-on/-off thresholds run input turn-on threshold, run rising run hysteresis l 1.08 1.2 130 1.32 v mv i run run leakage current run = 3.3v l 0.1 50 na oscillator and phase-locked loop (pll) f osc oscillator frequency accuracy v in = 12v, iseta = 5v, and: f set open circuit r fset = 57.6k (see f s specification) l 360 400 1.95 440 khz mhz f sync pll synchronization capture range v in = 12v, iseta = 5v, clkin driven with a gnd- referred clock toggling from 0.4v to 1.2v and having a clock duty cycle: from 10% to 90%; f set open circuit from 40% to 60%; r fset = 57.6k 250 1.3 550 3 khz mhz v clkin clkin input threshold v clkin rising v clkin falling 1.2 0.4 v v i clkin clkin input current v clkin = 5v v clkin = 0v C20 230 C5 500 a a power good feedback input and power good output ov pgdfb output overvoltage pgood upper threshold pgdfb rising l 620 645 675 mv uv pgdfb output undervoltage pgood lower threshold pgdfb falling l 525 555 580 mv ?v pgdfb pgood hysteresis pgdfb returning 8 mv r pgdfb resistor between pgdfb and sgnd 4.94 4.99 5.04 k r pgood pgood pull-down resistance v pgood = 0.1v, v pgdfb < uv pgdfb or v pgdfb > ov pgdfb 700 1500 i pgood(leak) pgood leakage current v pgood = 3.3v, uv pgdfb < v pgdfb < ov pgdfb 0.1 1 a t pgood(delay) pgood delay pgood low to high (note 4) pgood high to low (note 4) 16/f sw(hz) 64/f sw(hz) s s current monitor and input v oltage regulation pins h imona i out /i imona ratio of v out output current to i imona current, i out = 4a l 36 40 44 k i os(imon) i mona offset current i imona at i out = 0a C5 5 a i monb resistor resistor between i monb and sgnd 9.8 10 10.2 k v imona i mona servo voltage imona voltage during output current regulation l 1.9 2.0 2.1 v v vinreg vinreg servo voltage vinreg voltage during output current regulation l 1.8 2.0 2.2 v i vinreg vinreg leakage current vinreg = 2v 1 na intv cc regulator v intvcc channel internal v cc voltage, no intv cc loading (i intvcc = 0ma) 3.6v sv in 58v, extv cc = open circuit 5v sv in 58v, 3.2v extv cc 26.5v 3.15 2.85 3.4 3.0 3.65 3.15 v v v extvcc(th) extv cc switchover voltage (note 4) 3.15 v ?v intvcc(load) / v intvcc intv cc load regulation 0ma i intvcc 30ma C2 0.5 2 % electrical characteristics lt m4653 rev 0
5 for more information www.analog.com the l denotes the specifications which apply over the specified internal operating temperature range (note 2). t a = 25c, test circuit, v in = sv in = 48v, extv cc = 24v, run = 3.3v, r iset = 480k, r fset = 57.6k, f sw = 1.5mhz (clkin driven with 1.2mhz clock signal) unless otherwise noted. note 1: stresses beyond those listing under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating conditions for extended periods may affect device reliability and lifetime. note 2: the ltm4653 is tested under pulsed load conditions such that t j t a . the ltm4653e is guaranteed to meet performance specifications over the 0c to 125c internal operating temperature range. specifications over the full C40c to 125c internal operating temperature range are assured by design, characterization and correlation with statistical process controls.the ltm4653i is guaranteed to meet specifications over the full internal operating temperature range. note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal resistance and other environmental factors. note 3: see output current derating curves for different v in , v out , and t a , located in the applications information section. note 4: minimum on-time, v in overvoltage lockout and overvoltage lockout hysteresis, and extv cc switchover threshold are tested at wafer sort. note 5: to ensure minimum on time criteria is met, v out(0.5vdc) high-line regulation is tested at 13.2v in , with f set and clkin open circuit. see the applications information section. note 6. see applications information section for dropout criteria. note 7. this ic includes overtemperature protection that is intended to protect the device during momentary overload conditions. junction temperature will exceed 125c when overtemperature protection is active. continuous operation above the specified maximum operating junction temperature may impair device reliability. note 8. the intv cc abs max peak output current is specified as the sum of current drawn by circuits internal to the module biased off of intv cc and current drawn by external circuits biased off of intv cc . see the applications information section. symbol parameter conditions min typ max units temperature sensor ?v temp temperature sensor forward voltage, v temp + C v temp C i temp + = 100a and i temp C = C100a at t a = 25c 0.6 v tc ?v(temp) ?v temp temperature coefficient C2.0 mv/ c electrical characteristics lt m4653 rev 0
6 for more information www.analog.com typical performance characteristics t a = 25c, unless otherwise noted. efficiency vs load current at 5v in , forced continuous mode efficiency vs load current at 12v in , forced continuous mode efficiency vs load current at 15v in , forced continuous mode efficiency vs load current at 24v in , forced continuous mode efficiency vs load current at 36v in , forced continuous mode efficiency vs load current at 48v in , forced continuous mode 3.3v transient response, 48v in 12v transient response, 48v in 1v transient response, 24v in 1.2v out , 400khz 1.5v out , 400khz 1.8v out , 400khz 2.5v out , 400khz 3.3v out , 400khz 1.0v out , 400khz 65 70 75 80 85 90 95 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 efficiency (%) load current (a) 4653 g01 1.5v out , 400khz 1.8v out , 400khz 2.5v out , 400khz 3.3v out , 400khz 5.0v out , 400khz 1.2v out , 400khz 1.0v out , 400khz 65 70 75 80 85 90 95 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 efficiency (%) load current (a) 4653 g02 1.8v out , 400khz 2.5v out , 400khz 3.3v out , 400khz 5.0v out , 450khz 12v out , 500khz 1.5v out , 400khz 1.2v out , 400khz 1.0v out , 400khz 60 65 70 75 80 85 90 95 100 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 efficiency (%) load current (a) 4653 g03 2.5v out , 400khz 3.3v out , 400khz 5.0v out , 550khz 12v out , 800khz 15v out , 750khz 1.0v out , 400khz 1.2v out , 400khz 1.5v out , 400khz 1.8v out , 400khz 55 60 65 70 75 80 85 90 95 100 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 efficiency (%) load current (a) 4653 g04 5v out , 575khz 12v out , 1.1mhz 15v out , 1.2mhz 24v out , 1.2mhz 1.5v out , 400khz 1.8v out , 400khz 2.5v out , 400khz 55 60 65 70 75 80 85 90 95 100 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 efficiency (%) load current (a) 4653 g05 3.3v out , 400khz 3.3v out , 400khz 5.0v out , 600khz 12v out , 1.2mhz 15v out , 1.4mhz 24v out , 1.5mhz 2.5v out , 400khz 60 65 70 75 80 85 90 95 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 efficiency (%) load current (a) 4653 g06 40s/div v out 50mv/div ac-coupled i out 2a/div 4653 g07 figure 30 circuit, 48v in , c inh = c d = 4.7f, c out = 2 x 100f, r fset = n/a, r iset = 66.5k, c th = 10nf, r th = 604, r extvcc = n/a, c extvcc = n/a, 2a to 4a load step at 2a/s 40s/div v out 100mv/div ac-coupled i out 2a/div 4653 g08 figure 30 circuit, 48v in , c inh = c d = 4.7f, c out = 2 x 22f, r fset = 124k, r iset = 240k, c th = 10nf, r th = 562, r extvcc = 49.9, c extvcc = 1f, 2a to 4a load step at 2a/s 40s/div v out 50mv/div ac-coupled i out 2a/div 4653 g09 figure 30 circuit, 24v in , c inh = c d = 4.7f, c out = 3 x 100f, r fset = n/a, r iset = 20k, c th = 6.8nf, r th = 681, r extvcc = n/a, c extvcc = n/a, 2a to 4a load step at 2a/s lt m4653 rev 0
7 for more information www.analog.com typical performance characteristics t a = 25c, unless otherwise noted. start-up, no load start-up, 4a load start-up, pre-bias short circuit, no load short circuit, 4a load 2ms/div run 2v/div pgood 2v/div v out 5v/div 4653 g10 figure 30 circuit, 48v in , c inh = c d = 4.7f, c out = 2 x 22f, r fset = 124k, r iset = 240k, r pgdfb = 95.3k, c th = 10nf, r th = 562, r extvcc = 49.9, c extvcc = 1f, no load 2ms/div run 2v/div pgood 2v/div v out 5v/div 4653 g11 figure 30 circuit, 48v in , c inh = c d = 4.7f, c out = 2 x 22f, r fset = 124k, r iset = 240k, r pgdfb = 95.3k, c th = 10nf, r th = 562, r extvcc = 49.9, c extvcc = 1f, 3 resistive load 2ms/div run 2v/div pgood 2v/div v out 5v/div i diode 1ma/div 4653 g12 figure 30 circuit, 48v in , c inh = c d = 4.7f, c out = 2 x 22f, r fset = 124k, r iset = 240k, r pgdfb = 95.3k, c th = 10nf, r th = 562, r extvcc = 49.9, c extvcc = 1f, v out pre-biased to 5v through 1n4148 diode 10s/div v out 5v/div i in 1a/div 4653 g13 figure 30 circuit, 48v in , c inh = c d = 4.7f, c out = 2 x 22f, r fset = 124k, r iset = 240k, r pgdfb = 95.3k, c th = 10nf, r th = 562, r extvcc = 49.9, c extvcc = 1f, no load prior to application of output short-circuit 10s/div v out 5v/div i in 1a/div 4653 g14 figure 30 circuit, 48v in , c inh = c d = 4.7f, c out = 2 x 22f, r fset = 124k, r iset = 240k, r pgdfb = 95.3k, c th = 10nf, r th = 562, r extvcc = 49.9, c extvcc = 1f, 3 resistive load prior to application of output short-circuit lt m4653 rev 0
8 for more information www.analog.com pin functions v in ( a1-a3, b3): power input pins. apply input voltage and input decoupling capacitance directly between vin and a ground (pgnd) plane. v d ( a4, b4, c4): drain of the converter s primary switch - ing mosfet. apply at minimum one 4.7f high frequency ceramic decoupling capacitor directly from v d to pgnd. give this capacitor higher layout priority (closer proximity to the module) than any v in decoupling capacitors. sv in (c3): input voltage supply for small-signal circuits. sv in is the input to the intv cc ldo. connect sv in directly to v in . no decoupling capacitor is needed on this pin. pgnd ( a5, b5, c5, d5, e5, f5, g4-5, h3, h5, j3-5, k4- 5, l4-5): power ground pins of the ltm4653 . connect all pins to the applications pgnd plane. v out ( k1-3, l1-3): power output pins of the ltm4653. connect all pins to the application s power v out plane. apply the output filter capacitors and the output load between a power v out plane and the applications pgnd plane. gnd (d4): ground pin of the ltm4653. electrically con- nect to the applications pgnd plane. v osns ( g1, h1 ): output voltage sense and feedback signal. connect v osns to v out at the point of load (pol). pins g1 and h1 are electrically connected to each other internal to the module, and thus it is only necessary to connect one v osns pin to v out at the pol. the remaining v osns pin can be used for redundant connectivity or routed to an ict test point for design-for-test considerations, as desired. sgnd ( e4, g2, h2): signal ground pins of the ltm4653. connect pin h2 to pgnd directly under the ltm4653. the sgnd pins at locations e4 and g2 are electrically con - nected to each other internal to the module, and thus it is only necessary to connect one sgnd pin to pgnd under the module. the remaining sgnd pins can be used for redundant connectivity or routed to an ict test point for design-for -test considerations, as desired. run (f4): run control pin. a voltage above 1.2v com - mands the module to regulate its output voltage. under - voltage lockout (uvlo) can be implemented by connecting run to the midpoint node formed by a resistor -divider between v in and gnd. run features 130mv of hysteresis. see the applications information section. intv cc (g3): internal regulator, 3.3v nominal output. internal control circuits and mosfet-drivers derive pow- er from intv cc bias. when operating 3.1v < sv in 58v, an ldo generates intv cc from sv in when run is logic high (run > 1.2v). no external decoupling is required. when run is logic low (run - gnd < 1.2v ), the intv cc ldo is off, i.e., intv cc is unregulated. (also see extv cc .) extv cc (f3): external bias, auxiliary input to the intv cc regulator. when extv cc exceeds 3.2v and sv in exceeds 5v , the intv cc ldo derives power from extv cc bias instead of the sv in path. this technique can reduce ldo losses considerably, resulting in a corresponding reduc- tion in module junction temperature. for applications in which 4v v out 26.5v , connect extv cc to v out through a resistor. (see the applications information section for resistor value.) when taking advantage of this extv cc feature, locally decouple extv cc to pgnd with a 1f ce- ramicotherwise, leave extv cc open circuit. isetb (f1): 1.5nf soft-start capacitor. connect isetb to iseta to achieve default soft-start characteristics, if desired. see iseta. iseta ( f2): accurate 50a current source. positive input to the error amplifier. connect a resistor (r iset ) from this pin to sgnd to program the desired ltm4653 output volt - age, v out = r iset ? 50a . a capacitor can be connected from iseta to sgnd to soft-start the output voltage and reduce start-up inrush current. connect iseta to isetb in order to achieve default soft-start, if desired. (see isetb.) in addition, the output of the ltm4653 can track a voltage applied between the iseta pin and the sgnd pins. (see the applications information section.) package row and column labeling may vary among module products. review each package layout carefully. lt m4653 rev 0
9 for more information www.analog.com pgood (d1): power good indicator, open-drain output pin. pgood is high impedance when pgdfb is within approximately 7.5% of 0.6v. pgood is pulled to gnd when pgdfb is outside this range. pgdfb (d2): power good feedback programming pin. connect pgdfb to v osns through a resistor, r pgdfb . r pgdfb configures the voltage threshold of v out for which pgood toggles its state. if the pgood feature is used, set r pgdfb to: r pgdfb = v out 0.6v C 1 ? ? ? ? ? ? ? 4.99k otherwise, leave pgdfb open circuit. a small filter capacitor ( 220pf ) internal to the ltm4653 on this pin provides high frequency noise immunity for the pgood output indicator. f set (e3): oscillator frequency programming pin. the default switching frequency of the ltm4653 is 400khz. often, it is necessary to increase the programmed fre- quency by connecting a resistor between f set and sgnd. (see the applications information section.) note that the synchronization range of clkin is approximately 40% of the oscillator frequency programmed by the f set pin. clkin (b1): mode select and oscillator synchronization input. leave clkin open circuit for forced continuous mode operation. alternatively, this pin can be driven to synchronize the switching frequency of the ltm4653 to a clock signal. in this condition, the ltm4653 operates in forced continuous mode and the cycle-by-cycle turn- on of the primary power mosfet m t is coincident with the rising edge of the clock applied to clkin. note the synchronization range of clkin is approximately 40% of the oscillator frequency programmed by the f set pin. (see the applications information section.) compa (e2): current control threshold and error ampli- fier compensation node. the trip threshold of ltm4653s current comparator increases with a corresponding rise in compa voltage. a small filter cap (10pf) internal to the ltm4653 on this pin introduces a high-frequency roll- off of the error-amplifier response, yielding good noise rejection in the control-loop. compa is often electrically connected to compb in ones application, thus applying default loop compensation. loop compensation (a series resistor-capacitor) can be applied externally to compa if desired or needed, instead. (see compb.) compb (e1): internal loop compensation network. for most applications, the internal, default loop compensation of the ltm4653 is suitable to apply as is , and yields very satisfactory results : apply the default loop compensation to the control loop by simply connecting compa to compb. when more specialized applications require a personal touch to the optimization of control loop response, this can be accomplished by connecting a series resistor- capacitor network from compa to sgnd and leaving compb open circuit. vinreg (d3): input voltage regulation programming pin. optionally connect this pin to the midpoint node formed by a resistor-divider between v d and sgnd. when the voltage on vinreg falls below approximately 2v, a vinreg control loop servos v out to decrease the power inductor current and thus regulate vinreg at 2v. (see the applications information section.) if this input voltage regulation feature is not desired, con - nect vinreg to intv cc . imona (c2): power inductor current analog indicator pin and current limit programming pin. the current flowing out of this pin is equal to 1/40,000 of the average power inductor current. to construct a voltage (v imona ) that is proportional to the power inductor current, optionally apply a parallel resistor-capacitor network to this pin and terminate it to sgnd. imona can be connected to imonb if the default resis- tor-capacitor termination network provided by imonb is desired: 1v at full scale ( 4a ) load current. (see imonb.) if this analog indicator feature is not desired, connect imona to sgnd. if imona ever exceeds a trip threshold of approximately 2v , an imon control loop servos v out to decrease power inductor current and thus regulate imona at 2v. in this manner, the average current limit inception threshold of the ltm4653 can be configured. (see the applications information section.) pin functions lt m4653 rev 0
10 for more information www.analog.com imonb ( c1): power inductor analog indicator current de - fault termination r-c network. a 10k resistor in parallel with a 10nf capacitor and terminating to sgnd connect to this pin. connect imonb to imona to achieve default power inductor analog indicator current characteristics: 1v at full scale (4a) load current. (see imona.) temp+ ( j1, j6): temperature sensor, positive input. emitter of a 2n3906-genre pnp bipolar junction transis- tor (bjt). optionally interface to temperature monitor - ing circuitry such as ltc ? 2997, ltc2990, ltc2974 or ltc2975 . otherwise leave electrically open. pins j1 and j6 are electrically connected together internal to the ltm4653, and thus it is only necessary to connect one temp+ pin to monitoring circuitry. the remaining temp+ pin can be used for redundant connectivity or routed to an ict test point for design-for-test considerations, as desired. tempC ( j2, j7): temperature sensor, negative input. collector and base of a 2n3906-genre pnp bipolar junc- tion transistor (bjt). optionally interface to temperature monitoring circuitry such as ltc2997, ltc2990, ltc2974 or ltc2975 . otherwise leave electrically open. pins j2 and j7 are electrically connected together internal to the ltm4653 , and thus it is only necessary to connect one tempC pin to monitoring circuitry. the remaining tempC pin can be used for redundant connectivity or routed to an ict test point for design-for-test considerations, as desired. sw (h4): switching node of switching converter stage. used for test purposes. may be routed a short distance with a thin trace to a local test point to monitor switching action of the converter, if desired, but do not route near any sensitive signals; otherwise, leave electrically open circuit. nc ( a6-7, b2, b6-7, c6-7, d6-7, e6-7, f6-7, g6-7, h6-7, k6-7, l6-7): no connect pins, i.e., pins with no internal connection. the nc pins predominantly serve to provide improved mounting of the module to the board. in ones layout, nc pins are permitted to remain electrically uncon - nected or can be connected as desired, e.g., connected to a gnd plane for heat-spreading purposes and/or to facilitate routing. pin functions lt m4653 rev 0
11 for more information www.analog.com simplified block diagram + + v in 3.1v to 58v v out down to 0.5v up to 0.94 ? v in up to 4a load-local mlccs (high-frequency decoupling) c d 4.7f sv in v in v d v out v osns i l 40000 c outh c out m t m b pgnd pgnd pgood (centrally- located pnp temperature sensor) sgnd gnd sgnd imonb 400khz default imona vinreg compb compa iseta extv cc run clkin run - gnd: >1.2vtyp = on <1.07vtyp = off isetb 10k 10nf 1.5nf 10pf 50a 1f intv cc r iset r iset = pgdfb 4.99k 100 249k 10k 10nf 2v 220pf 4653 bd temp+ temp? sw 0.1f error amplifier to current comparators, pwm, and fet-drivers power control and anaolg circuits 0.1f 1 4h 0.1f 400nh bead c inl c inh load hi-z when v pgdfb -sgnd is within 0.6v7.5% r pgdfb + ? + ? + ? + ? f set v out 50a comp buffer pgood logic lt m4653 rev 0
12 for more information www.analog.com test circuit decoupling requirements application symbol parameter conditions min typ max units test circuit c inh , c d external high frequency input capacitor requirement, 28v v in 58v, v out = 24v i out = 4a 9.4 f c outh external high frequency output capacitor requirement 28v v in 58v, v out = 24v i out = 4a 22 f t a = 25c. refer to test circuit v in sv in run gnd clkin v out v osns pgnd pgood imona imonb isetb iseta temp+ temp? extv cc pgdfb 24v out , up to 4a c outl 68f c outh 27f sgnd r pgdfb 196k r iset 480k r fset 57.6k r th 499 c d 4.7 f x2 c inh 4.7 f c th 0.1 f v d intv cc vinreg 4653 tc01 nc sw ltm4653 compa compb f set v in 28v to 58v + load lt m4653 rev 0
13 for more information www.analog.com power module description the ltm4653 is a non-isolated switch mode dc/dc step- down power supply. it can provide up to 4a output current with a few external input and output capacitors. set by a single resistor, r iset , the ltm4653 regulates a positive output voltage, v out . v out can be set to as low as 0.5v to as high as 0.94v in . the ltm4653 operates from a positive input supply rail, v in , between 3.1v and 58v. the typical application schematic is shown in figure?30. the ltm4653 contains an integrated constant-frequency current mode regulator, power mosfets, power inductor, emi filter and other supporting discrete components. the nominal switching frequency range is from 400khz to 3mhz, and the default operating frequency is 400khz. it can be externally synchronized to a clock, from 250khz to 3mhz . see the applications information section. the ltm4653 supports internal and external control loop compensation. internal loop compensation is selected by connecting the compa and compb pins. using internal loop compensation, the ltm4653 has sufficient stability margins and good transient performance with a wide range of output capacitorseven ceramic-only output capacitors. for external loop compensation, see the applications information section. ltpowercad ? is available for transient load step and stability analysis. input filter and noise cancellation circuitry reduces noise-coupling to the modules inputs and outputs, ensuring the modules electromagnetic interference (emi) meets the limits of en55022 class b (see figures 4 to 6). pulling the run pin below 1.2v forces the ltm4653 into a shutdown state. a capacitor can be applied from iseta to sgnd to program the output voltage ramp-rate; or, the default ltm4653 ramp-rate can be set by connecting iseta to isetb ; or, voltage tracking can be implemented by interfacing rail voltages to the iseta pin. see the applications information section. multiphase operation can be employed by applying an external clock source to the ltm4653s synchronization input, the clkin pin. see the typical applications section. ldo losses within the module are reduced by connecting extv cc to v out through an rc-filter or by connecting extv cc to a suitable voltage source. operation imona is an analog output current indicator pin. it sources a current proportional to the ltm4653s load current. when imona is electrically connected to imonb, the voltage on the imona/imonb node is proportional to load currentwith 1v corresponding to 4a load. imona can be interfaced to an external parallel-rc network instead of the one provided by imonb. if imona ever exceeds 2v, a servo loop reduces the ltm4653s output current in order to keep imona at or below 2v . through this servo mechanism, a parallel rc network can be connected to imona to implement an average current limit functionif desired. when the feature is not needed, connect imona to sgnd. the ltm4653 also features a spare control pin called vinreg, with a 2v servo threshold, which can be used to reduce the input current draw during input line sag ( brownout ) conditions. connect vinreg to intv cc when this feature is not needed. temp+ and tempC pins give access to a diode-con - nected pnp transistor, making it possible to monitor the ltm4653s internal temperatureif desired. external component selection is primarily determined by the maximum load current and output voltage. refer to table? 7 and the test circuit for recommended external component values. v in to v out step-down ratios there are restrictions on the v in to v out step-down ratio that the ltm4653 can achieve. the maximum duty cycle of the ltm4653 is 96% typical. the v in to v out mini- mum dropout voltage is a function of load current when operating in high duty cycle applications. as an example, v out(24vdc) from the electrical characteristics table high - lights the ltm4653s ability to regulate 24v out at up to 4a from 28v in , when running at a switching frequency, f sw , of 1.5mhz. at very low duty cycles, the ltm4653s on-time of m t each switching cycle should be designed to exceed the ltm4653 control loops specified minimum on-time of 60ns, t on(min) , (guardband to 90ns), i.e.: d f sw > t on(min) lt m4653 rev 0
14 for more information www.analog.com where d (unitless) is the duty-cycle of m t , given by: d = v out v in in rare cases where the minimum on-time restriction is violated, the frequency of the ltm4653 automatically and gradually folds back down to approximately one-fifth of its programmed switching frequency to allow v out to remain in regulation. see the frequency adjustment section. be reminded of notes 2, 3 and 5 in the electrical characteristics section regarding output current guidelines. input capacitors the ltm4653 achieves low input conducted emi noise due to tight layout and high-frequency bypassing of mosfets m t and m b within the module itself. a small filter inductor (400nh) is integrated in the input line (from v in to v d ), providing further noise attenuationagain, local to the switching mosfets. the v d and v in pins are available for external input capacitorsc d and c inh to form a high-frequency filter. as shown in the simplified block diagram, the ceramic capacitor c d on the ltm4653 s v d pins handles the majority of the rms current into the dc/ dc converter power stage and requires careful selection, for that reason. see figures 4 to 6 for demonstration of ltm4653s emi performance, meeting the radiated emissions requirements of en55022b. the input capacitance, c d , is needed to filter the pulsed current drawn by m t . to prevent excessive voltage sag on v d , a low-effective series resistance (low-esr, such as an x7r ceramic) input capacitor should be used, sized appropriately for the maximum c d rms ripple current: i cd(rms) = i out(max) % is the estimated efficiency of the power module. (see typical performance characteristics graphs.) several capacitors may be paralleled to meet the applica - tions target size, height, and c d rms ripple current rating. for lower input voltage applications, sufficient bulk input capacitance is needed to counteract line sag and transient operation effects during output load changes. the bulk capacitor can be a switcher-rated aluminum electrolytic capacitor or a polymer capacitor. suggested values for c d and c inh are found in table?7. a final precaution regarding ceramic capacitors concerns the maximum input voltage rating of the ltm4653s v in , sv in , and v d pins. a ceramic input capacitor combined with trace or cable inductance forms a high q (underdamped) tank circuit. if the ltm4653 circuit is plugged into a live supply, the input voltage can ring to twice its nominal value, possibly exceeding the devices rating. this situa - tion is easily avoided; see the hot-plugging safely section. output capacitors output capacitors c outh and c outl are applied to v out of the ltm4653 . sufficient capacitance and low esr are called for, to meet the output voltage ripple, loop stability, and transient requirements. c outl can be a low esr tantalum or polymer capacitor. c outh is a ceramic capacitor. the typical output capacitance is 22f (type x5r material, or better), if ceramic-only output capacitors are used. table?7 shows a matrix of suggested output capacitors optimized for 2a transient step-loads applied at 2a/s. additional output filtering may be required by the system designer, if further reduction of output ripple or dynamic transient spike is required. the ltpowercad design tool is available for transient and stability analysis. stability criteria are considered in the table?7 matrix, and ltpowercad is available for stability analysis. multiphase operation will reduce effective output ripple as a function of the num - ber of phases. application note 77 discusses this noise reduction versus output ripple current cancellation, but the output capacitance should be considered carefully as a function of stability and transient response. ltpowercad can be used to calculate the output ripple reduction as the number of implemented phases increases by n times. external loop compensation can be applied to compa if needed, for transient response optimization. forced continuous operation leave the clkin pin open circuit to command the ltm4653 for forced continuous operation. in this mode, the control loop is allowed to command the inductor peak current to lt m4653 rev 0
15 for more information www.analog.com operation approximately C1a , allowing for significant negative aver - age current. clocking the clkin pin at a frequency within 40% of the target switching frequency commanded by the f set pin synchronizes m t s turn-on to the rising edge of the clkin pin. output voltage programming, tracking and soft-start the ltm4653 regulates its output voltage, v out , accord- ing to the differential voltage present across iseta and sgnd. in most applications, the output voltage is set by simply connecting a resistor , r iset , from iseta to sgnd, according to: r iset = v out 50a since the ltm4653 control loop servos its output volt - age according to the voltage between iseta and sgnd : placing a capacitor , c ss , parallel to r set configures the ramp-up rate of iseta and thus v out . in the time domain, the output voltage ramp-up after the run pin is toggled from low to high (t = 0s) is given by: v out (t) = i iseta ? r iset ? 1C e C t r iset ? c ss ? ? ? ? ? ? ? ? ? ? the soft-start time, t ss , is defined as the time it takes for v out to ramp from 0v to 90% of its final value: t ss = Cr iset ? c ss ?in (1C 0.9 ) or t ss = 2.3 ? r iset ? c ss a default value of c ss = 1.5nf can be implemented by connecting iseta to isetb. for other ramp-up rates, connect an external c ss capacitor parallel to r iset . when starting up into a pre-biased v out , the ltm4653 stays in a sleep mode, keeping m t and m b off until v iseta equals v osns after which, the dc/dc converter commences switching action and v out is ramped according to the voltage commanded by iseta. since the ltm4653 control loop servos its v osns voltage to match that of iseta s, the ltm4653s output can be configured to track any voltage applied to iseta, refer - enced to sgnd. frequency adjustment the default switching frequency (f sw ) of the ltm4653 is 400khz . this is suitable for low-v in (v in 5v ) ap - plications and low-v out (v out 3.3v) applications. for a practical design, the ltm4653s inductor ripple current ( ? i pk-pk ) is suggested to be less than ~2a pk-pk . choose f sw according to: f sw = v out ? 1 ? d ( ) l ? ?i pk-pk where the value of ltm4653 s power inductor, l, is 4h. to avoid cycle-skipping, impose restrictions on f sw , to ensure minimum on time criteria is met: f sw < d t on(min) the ltm4653 s minimum on-time, t on(min) , is specified as 60ns . for a practical design, it is recommended to guardband to 90ns. to configure the ltm4653 for a higher switching frequency than its default of 400khz , apply a resistor, r fset , between the f set pin and sgnd. r fset is given (in m) by: r fset (m? ) = 1 10pf ?[f sw (mhz) C 0.4(mhz)] the relationship of r fset to programmed f sw is shown in figure?1. see table?7 for recommended f sw and cor - responding r fset values for various combinations of v in and v out . figure?1. relationship between r fset and target f sw lt m4653 rev 0 10 programmed switching frequency (mhz) 4653 f01 rf set not used rf set (k) 10 100 1k 10k 0.1 1
16 for more information www.analog.com power module protection the ltm4653 s current mode control architecture provides fast cycle-by-cycle current limit in an overcurrent condition, as shown in the typical performance characteristics sec - tion. if the output voltage collapses sufficiently due to an overload or short-cir cuit condition, minimum on-time will be violated and the internal oscillator will then fold-back automatically to one-fifth of the ltm4653s programmed switching frequency thereby reducing the output current and affording the load a chance to recover. the ltm4653 features input overvoltage shutdown protec - tion: when v in > 68v , switching action ceases (with 4v of hysteresis) however, be advised that this protection is only active outside the ltm4653 s safe operating area (see note 1 and note 4 of the electrical characteristics table). the ltm4653 ceases switching action if internal tempera - tures exceed 165c. the control ic resumes operation after a 10c cool-down hysteresis. note that these typical parameters are based on measurements in a lab oven and are not production tested. this overtemperature protection is intended to protect the device during momentary over - load conditions. the maximum rated junction temperature will be exceeded when this overtemperature protection is active. continuous operation above the specified absolute maximum operating junction temperature may impair device reliability or permanently damage the device. the lt m4653 does not feature any specialized output overvoltage protection beyond what is inherent to the control loops servo mechanism. run pin enable the run pin is used to enable the power module or se - quence the power module. the threshold is 1.2v. the run pin can be used to provide an under voltage lockout (uvlo) function by connecting a resistor divider from the input supply to the run pin, as shown in figure?2. undervoltage lockout keeps the ltm4653 in shutdown until the supply input voltage is above a certain voltage programmed by the user. the run pin hysteresis voltage prevents noise applications information from falsely tripping uvlo. resistors are chosen by first selecting r b (refer to figure?2). then: r a = r b ? v in(on) 1.2v C 1 ? ? ? ? ? ? where v in(on) is the input voltage at which the undervolt - age lockout is overcome and the supply turns on. r a may be replaced with a hardwired connection from v d to run. the v in turn-off voltage, v in(off) is given by: v in(off) = 1.07v ? r a r b + 1 ? ? ? ? ? ? if uvlo is not needed, run can be connected to ltm4653 s v d or v in pins. when run is below its threshold, uvlo is engaged, m t and m b are turned off, intv cc ceases to be regulated, and iseta is discharged to sgnd by internal circuitry. loop compensation external loop compensation may be preferred for some applications and can be implemented easily, as follows : leave compb open circuit ; connect a series-r c network (r th and c th ) from compa to sgnd; in some instances, connect a capacitor (c thp ) from compa to sgnd (paral- leling the r th-cth series-rc network). see table? 7 for suggested input and output capacitances for a variety of operating conditions. additionally, the ltpowercad design tool is available for transient and stability analysis. run pin r a r b v supply 4653 f02 figure?2. undervoltage lockout resistive divider lt m4653 rev 0
17 for more information www.analog.com applications information hot-plugging safely the small size, robustness and low impedance of ceramic capacitors make them an attractive option for the input bypass capacitors (c d and c inh ) of the ltm4653 . however, these capacitors can cause problems if the ltm4653 is plugged into a live supply (see linear technology ap - plication note 88 for a complete discussion). the low loss ceramic capacitor combined with stray inductance in series with the power source forms an under damped tank cir cuit, and the voltage at the v in pin of the ltm4653 can ring to twice the nominal input voltage, possibly ex - ceeding the ltm4653s rating and damaging the part. if the input supply is poorly controlled or the user will be plugging the ltm4653 into an energized supply, the input network should be designed to prevent this overshoot by introducing a damping element into the path of current flow. this is often done by adding an inexpensive elec - trolytic bulk capacitor (c inl ) across the input terminals of the ltm4653. the selection criteria for c inl calls for: an esr high enough to damp the ringing; a capacitance value several times larger than c inh . c inl does not need to be located physically close to the ltm4653; it should be located close to the application board s input connec - tor, instead. intv cc and extv cc connection when run is logic high, an internal low dropout regula - tor regulates an internal supply, intv cc , that powers the control circuitry for driving ltm4653 s internal mosfets. intv cc is regulated at 3.3v . in this manner, the ltm4653s intv cc is directly powered from sv in , by default. the gate driver current through the ldo is about 20ma for a typical 1mhz application. the internal ldo power dissipation can be calculated as: p ldo _ loss(intvcc) = 20ma ? (sv in C 3v ) the ldo draws current off of extv cc instead of sv in when extv cc is higher than 3.2v and sv in is above 5v. for output voltages of 4v and higher, extv cc can be con - nected to v out through an rc-filter. when the internal ldo derives power from extv cc instead of sv in , the internal ldo power dissipation is: p ldo _ loss(extvcc) = 20ma ? (v out ? 3v ) the recommended value of the resistor between v out and extv cc is roughly v out ? 4 /v. this resistor, r extvcc , must be rated to continually dissipate (0.02a) 2 ? r extvcc . the primary purpose of this resistor is to prevent extv cc overstress under a fault condition. for example, when an inductive short-circuit is applied to the module s output, v out may be briefly dragged below pgnd forward bias - ing the pgnd-to-extv cc body diode. this resistor limits the magnitude of current flow in extv cc . bypass extv cc with 1f of x5r (or better) mlcc. multiphase operation multiple ltm4653 devices can be paralleled for higher output current applications. for lowest input and output voltage and current ripples, it is advisable to synchronize paralleled ltm4653 s to an external clock (within 40% of the target switching frequency set by f set see test circuit?1). see figure?32 for an example of a synchroniz - ing circuit. lt m4653 modules can be paralleled without synchronizing circuits: just be aware that some beat-frequency ripple will be present in the output voltage and reflected input current by virtue of the fact that such modules are not operating at identical, synchronized switching frequencies. the ltm4653 device is an inherently current mode con - trolled device, so parallel modules will have good current sharing s shown in figure? 33. this helps balance the thermals on the design. to parallel ltm4653s, connect the respective compa, iseta, and v osns pins of each ltm4653 together to share the current evenly. in addition, tie the respective run pins of paralleled ltm4653 devices together, to ensure proper start-up and shutdown behavior. figure?32 shows a schematic of ltm4653 devices operating in parallel. note that for parallel applications, v out can be set by a single, common resistor on the iseta net: r iset = v out 50a ? n where n is the number of ltm4653 modules in parallel configuration. lt m4653 rev 0
18 for more information www.analog.com applications information depending on the duty cycle of operation, the output volt- age ripple achieved by paralleled, synchronized ltm4653 modules may be considerably smaller than what is yielded by a single-phase solution. application note 77 provides a detailed explanation of multiphase operation (relevant to parallel ltm4653 applications) pertaining to noise reduction and output and input ripple current cancella - tion. regardless of ripple current cancellation, it remains important for the output capacitance of paralleled ltm4653 applications to be designed for loop stability and transient response. ltpowercad is available for such analysis. figure?3 illustrates the rms ripple current reduction as a function of the number of interleaved (paralleled and synchronized) ltm4653 modules derived from ap - plication note 77. radiated emi noise the generation of radiated emi noise is an inherent disad - vantage of switching regulators. fast switching turn-on and turn-off of the power mosfet s necessary for achieving high efficiencycreate high-frequency ( ~30mhz+) ?l/?t changes within dc/dc converters. this activity tends to be the dominant source of high-frequency emi radiation in such systems. the high level of device integration within ltm4653 including optimized gate-driver and critical front-end ? filter inductordelivers low radiated emi noise performance. figures 4 to 6 show typical ex - amples of ltm4653 meeting the radiated emission limits established by en55022 class b. thermal considerations and output current derating the thermal resistances reported in the pin configuration section of this data sheet are consistent with those pa - rameters defined by je sd51 -12 and are intended for use with finite element analysis (fea) software modeling tools that leverage the outcome of thermal modeling, simula - tion, and correlation to hardware evaluation performed on a module package mounted to a hardware test board. the motivation for providing these thermal coefficients is found in je sd51 -12 (guidelines for reporting and using electronic package thermal information). many designers may opt to use laboratory equipment and a test vehicle such as the demo board to predict the module regulator s thermal performance in their application at various electrical and environmental operating conditions to compliment any fea activities. without fea software, the thermal resistances reported in the pin configuration section are, in and of themselves, not relevant to providing guidance of thermal performance ; instead, the derating curves provided in this data sheet can be used in a man - ner that yields insight and guidance pertaining to ones application-usage, and can be adapted to correlate thermal per formance to ones own application. the pin configuration section gives four thermal coeffi - cients explicitly defined in jesd51-12; these coefficients are quoted or paraphrased below : 1. ja , the thermal resistance from junction to ambient, is the natural convection junction-to-ambient air thermal resistance measured in a one cubic foot sealed enclo - sure. this environment is sometimes referred to as still air although natural convection causes the air to move. this value is determined with the part mounted to a jesd51 -9 defined test board, which does not reflect an actual application or viable operating condition. 2. jcbottom , the thermal resistance from junction to the bottom of the product case, is determined with all of the component power dissipation flowing through the bottom of the package. in the typical module regulator, the bulk of the heat flows out the bottom of the pack - age, but there is always heat flow out into the ambient environment. as a result, this thermal resistance value may be useful for comparing packages but the test conditions don t generally match the users application. 3. jctop , the thermal resistance from junction to top of the product case, is determined with nearly all of the component power dissipation flowing through the top of the package. as the electrical connections of the typical module regulator are on the bottom of the package, it is rare for an application to operate such that most of the heat flows from the junction to the top of the part. as in the case of jcbottom , this value may be useful for comparing packages but the test conditions dont generally match the users application. lt m4653 rev 0
19 for more information www.analog.com applications information figure?3. normalized input rms ripple current vs duty cycle for one to six ltm4653s (phases) figure?4. radiated emissions scan of the ltm4653. producing 24v out at 4a, from 29.5v in . dc2327a hardware. f sw = 1.2mhz. measured in a 10m chamber. peak detect method 0.75 0.8 4653 f03 0.70.650.60.550.50.450.40.350.30.250.20.150.1 0.85 0.9 duty cycle 0 dc load current rms input ripple current 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 0.55 0.60 1-phase 2-phase 3-phase 4-phase 6-phase amplitude (dbv/m) 50 60 70 40 30 20 10 ? 10 0 frequency (mhz) 30 830 130 230 330 430 530 630 730 930 1000 4653 f04 [1] horizontal [2] vertical qpk limit formal meas dist 10m spec dist 10m + amplitude (dbv/m) 50 60 70 40 30 20 10 ? 10 0 frequency (mhz) 30 830 130 230 330 430 530 630 730 930 1000 4653 f05 [1] horizontal [2] vertical qpk limit formal meas dist 10m spec dist 10m + amplitude (dbv/m) 50 60 70 40 30 20 10 ? 10 0 frequency (mhz) 30 830 130 230 330 430 530 630 730 930 1000 4653 f06 [1] horizontal [2] vertical qpk limit formal meas dist 10m spec dist 10m + figure?5. radiated emissions scan of the ltm4653 producing 24v out at 3.5a, from 48v in . dc2327a hardware. f sw = 1.2mhz. measured in a 10m chamber. peak detect method figure?6. radiated emissions scan of the ltm4653. producing 12v out at 3a, from 58v in . dc2327a hardware. f sw = 1.2mhz. measured in a 10m chamber. peak detect method lt m4653 rev 0
20 for more information www.analog.com 4. jb , the thermal resistance from junction to the printed circuit board, is the junction-to-board thermal resis - tance where almost all of the heat flows through the bottom of the module regulator and into the board, and is really the sum of the jcbottom and the thermal resistance of the bottom of the part through the solder joints and through a portion of the board. the board temperature is measured a specified distance from the package, using a two sided, two layer board. this board is described in jesd51-9. a graphical representation of the aforementioned ther - mal resistances is given in figure?7 ; blue resistances are contained within the module regulator, whereas green resistances are external to the module package. as a practical matter, it should be clear to the reader that no individual or sub-group of the four thermal resistance parameters defined by je sd51 -12 or provided in the pin configuration section replicates or conveys normal operating conditions of a module regulator. for example, in normal board-mounted applications, never does 100% of the devices total power loss (heat) thermally conduct exclusively through the top or exclusively through bot - tom of the module packageas the standard defines for jctop and jcbottom , respectively. in practice, power loss is thermally dissipated in both directions away from the package granted, in the absence of a heat sink and airflow, a majority of the heat flow is into the board. within the ltm4653, be aware there are multiple power devices and components dissipating power, with a con - sequence that the thermal resistances relative to different junctions of components or die are not exactly linear with respect to total package power loss. t o reconcile this complication without sacrificing modeling simplicity but also not ignoring practical realities an approach has been taken using fea software modeling along with laboratory testing in a controlled-environment chamber to reason - ably define and correlate the thermal resistance values supplied in this data sheet : (1) initially, fea software is used to accurately build the mechanical geometry of the ltm4653 and the specified pcb with all of the correct material coefficients along with accurate power loss sour ce definitions ; (2) this model simulates a software- defined jedec environment consistent with jesd51 -9 and jesd51 -12 to predict power loss heat flow and temperature readings at different inter faces that enable the calculation of the jedec-defined thermal resistance values ; (3) the model and fea software is used to evaluate the ltm4653 with heat sink and airflow ; (4) having solved for and analyzed these thermal resistance values and simulated various operating conditions in the software model, a thorough laboratory evaluation replicates the simulated conditions with thermocouples within a controlled envi - ronment chamber while operating the device at the same power loss as that which was simulated. the outcome of this process and due diligence yields the set of derating applications information 4653 f07 module device junction-to-case (top) resistance junction-to-board resistance junction-to-ambient thermal resistance components case (top)-to-ambient resistance board-to-ambient resistance junction-to-case (bottom) resistance junction ambient case (bottom)-to-board resistance figure?7. graphical representaion of jesd51-12 thermal coefficients lt m4653 rev 0
21 for more information www.analog.com curves provided in later sections of this data sheet, along with well-correlated jesd51- 12-defined values provided in the pin configuration section of this data sheet. the 1v , 5v , and 15v and 24v power loss curves in figures? 8, 9 and 10 respectively can be used in coordination with the load current derating curves in figures 11 to 28 for calculating an approximate ja thermal resistance for the lt m4653 with various heat sinking and air flow conditions. these thermal resistances represent demonstrated performance of the lt m4653 on dc2327 a hardware ; a 4- layer f r4 pcb measuring 99mm 133mm 1.6mm using outer and inner copper weights of 2oz and 1oz , respectively. the power loss curves are taken at room temperature, and are increased with multiplicative factors with ambient temperature. these approximate factors are listed in table?1 . (compute the factor by interpolation, for intermediate tem peratures.) the derating curves are plotted with the lt m4653 s output initially sourcing 4a and the ambient temperature at 20 c . the output voltages are 1v, 5v , 15v and 24v . these are chosen to include the lower and higher output voltage ranges for correlating the thermal resistance. in all derating curves, the switching frequency of operation follows guidance provided by table? 7. thermal models are derived from several temperature measurements in a controlled temperature chamber along with thermal modeling analysis. the junction temperatures are monitored while ambient temperature is increased with and without air flow, and with and without a heat sink attached with thermally conductive adhesive tape. the power loss increase with ambient temperature change is factored into the derating curves. the junctions are maintained at 120 c maximum while lowering output current or power while increasing ambient temperature. the decreased output current decreases the internal module loss as ambient temperature is increased. the monitored junction temperature of 120 c minus the ambient operating temperature specifies how much module temperature rise can be allowed. as an example in figure?25 , the load current is derated to 2.5a at 70c am bient with 200lfm airflow and no heat sink and the room temperature ( 25 c ) power loss for this 48v in to 24v out at 2.5a out condition is 3.9w . a 4.5w loss is calculated by multiplying the 3.9w room temperature loss from the 48v in to 24v out power loss curve at 2.5a ( figure? 10 ), with? the 1.15 multiplying factor at 70 c ambient (from table?1 ). if the 70 c ambient temperature is subtracted from the 120 c junction temperature, then the difference of 50 c divided by 4.5w yields a thermal resistance, ja , of 11. 1c /w in good agreement with table?4 . tables 2, 3 and 4 provide equivalent thermal resistances for 1v, 5v and 15v and 24v outputs with and without air flow and heat sinking. the derived thermal resistances in tables 2, 3 and 4 for the various conditions can be multiplied by the calculated power loss as a function of ambient temperature to derive temperature rise above ambient, thus maximum junction temperature. room temperature power loss can be derived from the efficiency curves in the typical performance characteristics section and adjusted with ambient temperature multiplicative factors from table?1. table?1. power loss multiplicative factors vs ambient temperature ambient temperature power loss multiplicative factor up to 40c 1.00 50c 1.05 60c 1.10 70c 1.15 80c 1.20 90c 1.25 100c 1.30 110c 1.35 120c 1.40 applications information lt m4653 rev 0
22 for more information www.analog.com table?2. 1v output derating curve v in (v) power loss curve airflow (lfm) heat sink ja (c/w) figures 11, 12, 13 5, 12, 24 figures 8, 9 0 none 13.9 figures 11, 12, 13 5, 12, 24 figures 8, 9 200 none 11.4 figures 11, 12, 13 5, 12, 24 figures 8, 9 400 none 10.7 figures 14, 15, 16 5, 12, 24 figures 8, 9 0 bga heat sink 13.3 figures 14, 15, 16 5, 12, 24 figures 8, 9 200 bga heat sink 11.0 figures 14, 15, 16 5, 12, 24 figures 8, 9 400 bga heat sink 10.3 table?3. 5v output derating curve v in (v) power loss curve airflow (lfm) heat sink ja (c/w) figures 17, 18, 19 12, 24, 48 figures 8, 9, 10 0 none 13.9 figures 17, 18, 19 12, 24, 48 figures 8, 9, 10 200 none 11.4 figures 17, 18, 19 12, 24, 48 figures 8, 9, 10 400 none 10.7 figures 20, 21, 22 12, 24, 48 figures 8, 9, 10 0 bga heat sink 13.3 figures 20, 21, 22 12, 24, 48 figures 8, 9, 10 200 bga heat sink 11.0 figures 20, 21, 22 12, 24, 48 figures 8, 9, 10 400 bga heat sink 10.3 table?4. 15v and 24v output derating curve v in (v) power loss curve airflow (lfm) heat sink ja (c/w) figures 23, 24, 25 24, 48 figures 9, 10 0 none 13.9 figures 23, 24, 25 24, 48 figures 9, 10 200 none 11.4 figures 23, 24, 25 24, 48 figures 9, 10 400 none 10.7 figures 26, 27, 28 24, 48 figures 9, 10 0 bga heat sink 13.3 figures 26, 27, 28 24, 48 figures 9, 10 200 bga heat sink 11.0 figures 26, 27, 28 24, 48 figures 9, 10 400 bga heat sink 10.3 table?5. heat sink manufacturer (thermally conductive adhesive tape pre-attached) heat sink manufacturer part number website cool innovations 3-0504035ut411 www.coolinnovations.com table?6. thermally conductive adhesive tape vendor thermally conductive adhesive tape manufacturer part number website chomerics t411 www.chomerics.com applications information lt m4653 rev 0
23 for more information www.analog.com applications information table?7. ltm4653 output voltage response vs component matrix. performance of figure?30 circuit with values here indicated. load-stepping from 2a to 4a load current, at 2a/s. typical measured values c outh vendors? part number? c outh vendors? part number? avx 12066d107mat2a (100f, 6.3v, 1206 case size) avx 12105d106mat2a (10f, 50v, 1210 case size) murata grm31cr60j107m (100f, 6.3v, 1206 case size) murata grm32er61h106m (10f, 50v, 1210 case size) taiyo yuden jmk316bbj107mlht (100f, 6.3v, 1206 case size) taiyo yuden umk325bj106m (10f, 50v, 1210 case size) tdk c3216x5r0j107m (100f, 6.3v, 1206 case size) tdk c3225x5r1h106m (10f, 50v, 1210 case size) avx 1210yd476mat2a (47f, 16v, 1210 case size) c inh /c d vendors? part number? murata grm32er61c476m (47f, 16v, 1210 case size) murata grm32er71k475m (4.7f, 80v, 1210 case size) taiyo yuden emk325bj476mm (47f, 16v, 1210 case size) avx 12065c475mat2a (4.7f, 50v, 1206 case size) avx 12103d226mat2a (22f, 25v, 1210 case size) murata grm31cr71h475m (4.7f, 50v, 1206 case size) taiyo yuden tmk325bj226mm (22f, 25v, 1210 case size) taiyo yuden umk316ab7475ml (4.7f, 50v, 1206 case size) tdk c3225x5r1e226m (22f, 25v, 1210 case size) tdk c3216x5r1h475m (4.7f, 50v, 1206 case size) v out (v) v in (v) c inh c d c outh r th () c th (nf) r iset (k) r pgdfb (k) f sw (khz) r fset (k) r extvcc () load step transient droop (mv) load step pk-pk deviation (mv) recover y time (s) 1 5 4.7f 4.7f 100f x 3 681 6.8 20 3.32 400 n/a n/a 70 145 55 1 12 4.7f 4.7f 100f x 3 681 6.8 20 3.32 400 n/a n/a 70 145 50 1 24 4.7f 4.7f 100f x 3 681 6.8 20 3.32 400 n/a n/a 70 145 50 1.2 5 4.7f 4.7f 100f x 3 665 6.8 24 4.99 400 n/a n/a 70 145 50 1.2 12 4.7f 4.7f 100f x 3 665 6.8 24 4.99 400 n/a n/a 70 145 50 1.2 24 4.7f 4.7f 100f x 3 665 6.8 24 4.99 400 n/a n/a 70 145 50 1.5 5 4.7f 4.7f 100f x 3 665 6.8 30.1 7.5 400 n/a n/a 70 145 50 1.5 12 4.7f 4.7f 100f x 3 665 6.8 30.1 7.5 400 n/a n/a 70 145 50 1.5 24 4.7f 4.7f 100f x 3 665 6.8 30.1 7.5 400 n/a n/a 70 145 50 1.5 36 4.7f 4.7f 100f x 3 665 6.8 30.1 7.5 400 n/a n/a 70 145 50 1.8 5 4.7f 4.7f 100f x 3 665 8.2 36 10 400 n/a n/a 70 145 50 1.8 12 4.7f 4.7f 100f x 3 665 8.2 36 10 400 n/a n/a 70 145 50 1.8 24 4.7f 4.7f 100f x 3 665 8.2 36 10 400 n/a n/a 70 145 50 1.8 36 4.7f 4.7f 100f x 3 665 8.2 36 10 400 n/a n/a 70 145 50 2.5 5 4.7f 4.7f 100f x 3 649 8.2 50 15.8 400 n/a n/a 70 145 50 2.5 12 4.7f 4.7f 100f x 3 649 8.2 50 15.8 400 n/a n/a 70 145 50 2.5 24 4.7f 4.7f 100f x 3 649 8.2 50 15.8 400 n/a n/a 70 145 50 2.5 36 4.7f 4.7f 100f x 3 649 8.2 50 15.8 400 n/a n/a 70 145 50 2.5 48 4.7f 4.7f 100f x 3 649 8.2 50 15.8 400 n/a n/a 70 145 50 3.3 5 4.7f 4.7f 100f x 2 604 10 66.5 22.6 400 n/a n/a 90 190 50 3.3 12 4.7f 4.7f 100f x 2 604 10 66.5 22.6 400 n/a n/a 90 190 50 3.3 24 4.7f 4.7f 100f x 2 604 10 66.5 22.6 400 n/a n/a 90 185 50 3.3 36 4.7f 4.7f 100f x 2 604 10 66.5 22.6 400 n/a n/a 90 180 50 3.3 48 4.7f 4.7f 100f x 2 604 10 66.5 22.6 400 n/a n/a 90 180 50 5 12 4.7f 4.7f 47f x 2 499 10 100 36.5 400 n/a 20 130 260 45 5 24 4.7f 4.7f 47f x 2 499 10 100 36.5 550 665 20 130 260 45 5 36 4.7f 4.7f 47f x 2 499 10 100 36.5 575 576 20 130 260 45 5 48 4.7f 4.7f 47f x 2 499 10 100 36.5 600 499 20 130 260 45 12 15 4.7f 4.7f 22f x 2 499 10 240 95.3 500 1000 49.9 170 350 40 12 24 4.7f 4.7f 22f x 2 499 10 240 95.3 800 249 49.9 170 350 40 12 36 4.7f 4.7f 22f x 2 499 10 240 95.3 1100 143 49.9 170 350 40 12 48 4.7f 4.7f 22f x 2 499 10 240 95.3 1200 124 49.9 170 350 40 15 24 4.7f 4.7f 22f x 2 499 10 301 121 750 287 60.4 170 350 40 15 36 4.7f 4.7f 22f x 2 499 10 301 121 1200 124 60.4 170 350 40 15 48 4.7f 4.7f 22f x 2 499 10 301 121 1400 100 60.4 170 350 40 24 36 4.7f 4.7f 10f x 2 499 10 481 196 1200 124 100 220 430 35 24 48 4.7f 4.7f 10f x 2 499 10 481 196 1500 90.9 100 220 440 35 lt m4653 rev 0
24 for more information www.analog.com applications information derating curves figure?8. 12v in power loss curve figure?9. 24v in power loss curve figure?10. 48v in power loss curve see table?1 for f sw and r extvcc . 0.0 0.5 1.0 1.5 2.0 2.5 3.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 power loss (w) output current (a) 4653 f08 1.5v out , 400khz 1.8v out , 400khz 2.5v out , 400khz 3.3v out , 400khz 5.0v out , 400khz 1.2v out , 400khz 1.0v out , 400khz 0.0 0.5 1.5 1.0 2.0 3.5 3.0 2.5 4.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 power loss (w) output current (a) 4653 f09 2.5v out , 400khz 3.3v out , 400khz 5.0v out , 550khz 12v out , 800khz 15v out , 750khz 1.8v out , 400khz 1.5v out , 400khz 1.2v out , 400khz 1.0v out , 400khz 0.0 1.0 2.0 5.0 4.0 3.0 6.0 7.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 power loss (w) output current (a) 4653 f10 3.3v out , 400khz 5.0v out , 600khz 12v out , 1.2mhz 15v out , 1.4mhz 24v out , 1.5mhz 2.5v out , 400khz 20 40 60 80 100 120 ambient temperature (c) 4653 f12 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 maximum load current (a) 400lfm 200lfm olfm 20 40 60 80 100 120 ambient temperature (c) 4653 f13 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 maximum load current (a) 400lfm 200lfm olfm 20 40 60 80 100 120 ambient temperature (c) 4653 f14 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 maximum load current (a) 400lfm 200lfm olfm 20 40 60 80 100 120 ambient temperature (c) 4653 f15 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 maximum load current (a) 400lfm 200lfm olfm 20 40 60 80 100 120 ambient temperature (c) 4653 f16 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 maximum load current (a) 400lfm 200lfm olfm 20 40 60 80 100 120 ambient temperature (c) 4653 f11 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 maximum load current (a) 400lfm 200lfm olfm figure?11. 5v to 1v out derating curve, no heat sink figure?12. 12v to 1v out derating curve, no heat sink figure?13. 24v to 1v out derating curve, no heat sink figure?14. 5v to 1v out derating curve, with bga heat sink figure?15. 12v to 1v out derating curve, with bga heat sink figure?16. 24v to 1v out derating curve, with bga heat sink lt m4653 rev 0
25 for more information www.analog.com figure?17. 12v to 5v out derating curve, no heat sink applications information derating curves s t s r extvcc 20 40 60 80 100 120 ambient temperature (c) 4653 f17 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 maximum load current (a) 400lfm 200lfm olfm 20 40 60 80 100 120 ambient temperature (c) 4653 f18 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 maximum load current (a) 400lfm 200lfm olfm 20 40 60 80 100 120 ambient temperature (c) 4653 f19 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 maximum load current (a) 400lfm 200lfm olfm 20 40 60 80 100 120 ambient temperature (c) 4653 f20 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 maximum load current (a) 400lfm 200lfm olfm 20 40 60 80 100 120 ambient temperature (c) 4653 f21 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 maximum load current (a) 400lfm 200lfm olfm 20 40 60 80 100 120 ambient temperature (c) 4653 f22 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 maximum load current (a) 400lfm 200lfm olfm 20 40 60 80 100 120 ambient temperature (c) 4653 f23 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 maximum load current (a) 400lfm 200lfm olfm 20 40 60 80 100 120 ambient temperature (c) 4653 f24 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 maximum load current (a) 400lfm 200lfm olfm 20 40 60 80 100 120 ambient temperature (c) 4653 f25 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 maximum load current (a) 400lfm 200lfm olfm figure?18. 24v to 5v out derating curve, no heat sink figure?19. 48v to 5v out derating curve, no heat sink figure?20. 12v to 5v out derating curve, with bga heat sink figure?21. 24v to 5v out derating curve, with bga heat sink figure?22. 48v to 5v out derating curve, with bga heat sink figure?23. 24v to 15v out derating curve, no heat sink figure?24. 48v to 15v out derating curve, no heat sink figure?25. 48v to 24v out derating curve, no heat sink lt m4653 rev 0
26 for more information www.analog.com figure?26. 24v to 15v out derating curve, with bga heat sink figure?27. 48v to 15v out derating curve, with bga heat sink figure?28. 48v to 24v out derating curve, with bga heat sink applications information derating curves applications information safety considerations the ltm4653 does not provide galvanic isolation from v in to v out . there is no internal fuse. if required, a slow blow fuse with a rating twice the maximum input current needs to be provided to protect the unit from catastrophic failure. the fuse or circuit breaker, if used, should be selected to limit the current to the regulator in case of a m t mosfet fault. if m t fails, the system s input supply will source very large currents to v out through m t . this can cause excessive heat and board damage depending on how much power the input voltage can deliver to this system. a fuse or circuit breaker can be used as a secondary fault protector in this situation. the ltm4653 does feature overcurrent and overtemperature protection. layout checklist/example the high integration of ltm4653 makes the pcb board layout straightforward. however, to optimize its electrical and thermal performance, some layout considerations are still necessary. ? use large pcb copper areas for high current paths, including v in , pgnd and v out . doing so helps to minimize the pcb conduction loss and thermal stress. ? place high frequency ceramic input and output ca- pacitors next to the v in , v d , pgnd and v out pins to minimize high frequency noise. ? place a dedicated power ground layer underneath the ltm4653. ? to minimize the via conduction loss and reduce module thermal stress, use multiple vias for interconnection between top layer and other power layers. ? do not put vias directly on pads, unless they are capped or plated over. ? use a separate sgnd copper plane for components connected to signal pins. connect sgnd to pgnd directly under the module. ? for parallel module applications, connect the v out , v osns , run, iseta, compa and pgood pins together as shown in figure?32. ? bring out test points on the signal pins for monitoring. figure? 29 gives a good example of the recommended ltm4653 layout. 20 40 60 80 100 120 ambient temperature (c) 4653 f26 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 maximum load current (a) 400lfm 200lfm olfm 20 40 60 80 100 120 ambient temperature (c) 4653 f27 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 maximum load current (a) 400lfm 200lfm olfm 20 40 60 80 100 120 ambient temperature (c) 4653 f28 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 maximum load current (a) 400lfm 200lfm olfm see table?1 for f sw and r extvcc . lt m4653 rev 0
27 for more information www.analog.com applications information figure?29. recommend pcb layout, package top view typical applications figure?30. 4a, 24v output dc/dc module regulator gnd v in v out gnd 4653 f29 v in sv in v d run gnd v out v osns pgnd pgood imona imonb isetb iseta temp+ temp? extv cc pgdfb 24v out , up to 4a c outh 10f x2 sgnd r pgdfb 196k r pgdpup 100k r extvcc 100 c extvcc 1f 0.1f 470pf r iset 481k r fset 90.9k c d 4.7 f c inh 4.7 f intv cc intv cc intv cc c th 10nf vinreg clkin 4653 f30 nc sw ltm4653 optional analog output temperature indicator compa compb f set v in 48v load d + d ? v cc v ref v ptat gnd ltc2997 4mv/k r th 499 lt m4653 rev 0
28 for more information www.analog.com figure?31. start-up waveforms at 48v in , figure?30 circuit figure?32. 24v output at up to 8a from 48v input, 2-phase paralled with analog output current indicator typical applications iseta isetb u2 ltm4653 r fset 90.9k r iset 240k c th 10nf r th 499 f set 4653 f32 iseta isetb u1 ltm4653 24v out up to 8a load r fset1 90.9k c d 4.7 f c inh 4.7 f f set c inh 4.7 f c d 4.7 f r pgdfb1 196k r extvcc 100 r pgdpup 100 c extvcc 1f c out 22f 2 out1 out2 mod v in 48v v + set gnd ltc6908-1 r set 66.5k intv cc1 0.1f r extvcc 100 c extvcc 1f r pgdfb2 196k v out i out1 v osns extv cc sgnd pgnd pgdfb pgood pgood analog output current indicator v imon = 0.125 ? (i out1 + i out2 ) imona imonb temp+ temp? compa compb vinreg intv cc clkin gnd run nc sw v d sv in v in v out v osns pgnd pgdfb imona imonb pgood sgnd extv cc temp + temp ? compa compb vinreg intv cc clkin gnd run nc sw v d sv in v in intv cc1 i out2 lt m4653 rev 0 1ms/div v out 10v/div pgood 5v/div run 5v/div 4653 f31
29 for more information www.analog.com figure?33. current sharing performance of ltm4653s in figure?32 circuit figure?34. concurrent 12v supply, output voltage start-up waveforms, figure?35 circuit typical applications 0 1 2 3 4 5 6 7 8 total output current (a) 4653 f33 ?1 0 1 2 3 4 5 module output current (a) u2 u1 2ms/div v out 5v/div v out ? 5v/div pgood 5v/div run 5v/div lt m4653 rev 0 4653 f34
30 for more information www.analog.com package description table 9. ltm4653 component bga pinout pin id function pin id function pin id function pin id function pin id function pin id function a1 v in b1 clkin c1 imonb d1 pgood e1 compb f1 isetb a2 v in b2 nc c2 imona d2 pgdfb e2 compa f2 iseta a3 v in b3 v in c3 sv in d3 vinreg e3 f set f3 extv cc a4 v d b4 v d c4 v d d4 gnd e4 sgnd f4 run a5 pgnd b5 pgnd c5 pgnd d5 pgnd e5 pgnd f5 pgnd a6 nc b6 nc c6 nc d6 nc e6 nc f6 nc a7 nc b7 nc c7 nc d7 nc e7 nc f7 nc pin id function pin id function pin id function pin id function pin id function g1 v osns h1 v osns j1 temp + k1 v out l1 v out g2 sgnd h2 sgnd j2 temp C k2 v out l2 v out g3 intv cc h3 pgnd j3 pgnd k3 v out l3 v out g4 pgnd h4 sw j4 pgnd k4 pgnd l4 pgnd g5 pgnd h5 pgnd j5 pgnd k5 pgnd l5 pgnd g6 nc h6 nc j6 temp + k6 nc l6 nc g7 nc h7 nc j7 temp C k7 nc l7 nc package photograph lt m4653 rev 0
31 for more information www.analog.com package description package top view 4 pin ?a1? corner y x aaa z aaa z bga package 77-lead (15.00mm 9.00mm 5.01mm) (reference ltc dwg# 05-08-1826 rev ?) notes: 1. dimensioning and tolerancing per asme y14.5m-1994 2. all dimensions are in millimeters ball designation per jesd ms-028 and jep95 4 3 details of pin #1 identifier are optional, but must be located within the zone indicated. the pin #1 identifier may be either a mold or marked feature detail a ?b (77 places) a detail b package side view m x yzddd m zeee a2 d e bga 77 0417 rev ? tray pin 1 bevel package in tray loading orientation component pin ?a1? ltmxxxxxx module detail a package bottom view 3 see notes a b c d e f g h j k l pin 1 e b f g 7 6 5 4 3 2 1 suggested pcb layout top view 0.000 2.540 3.810 5.080 6.350 1.270 3.810 2.540 1.270 5.080 6.350 3.810 2.540 1.270 3.810 2.540 1.270 0.3175 0.3175 0.000 0.630 0.025 ? 77x 6 see notes 5. primary datum -z- is seating plane 6 package row and column labeling may vary among module products. review each package layout carefully ! symbol a a1 a2 b b1 d e e f g h1 h2 aaa bbb ccc ddd eee min 4.81 0.50 4.31 0.60 0.60 0.36 3.95 nom 5.01 0.60 4.41 0.75 0.63 15.00 9.00 1.27 12.70 7.62 0.41 4.00 max 5.21 0.70 4.51 0.90 0.66 0.46 4.05 0.15 0.10 0.20 0.30 0.15 total number of balls: 77 dimensions notes ball ht ball dimension pad dimension substrate thk mold cap ht z detail b substrate a1 ccc z z // bbb z h2 h1 b1 mold cap please refer to http://www.linear.com/product/ltm4653#packaging for the most recent package drawings. information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. lt m4653 rev 0
32 for more information www.analog.com ? analog devices, inc. 2018 d16803-0-4/18(0) www.analog.com related parts typical application figure?35. concurrent 12v supply. see figure?34 for output voltage start-up waveforms v out v osns sgnd pgnd pgdfb imona imonb isetb iseta temp+ temp? pgood extv cc intv cc f set compa compb clkin run gnd nc sw v d sv in v in vinreg u1 ltm4653 u2 ltm4651 v out 12v up to 4a r pgdfb1 95.3k r pgdpup 100 c outh 22f 2 intv cc1 i out load pgood analog output current indicator, v imon = 0.25 ? i out r extvcc1 49.9 c extvcc1 1f r fset1 124k c th 10nf r th 499 r iset1 240k c ss 10nf c inh1 4.7 f r a 105k c d1 4.7 f intv cc1 v in 15v to 46v c inout 4.7f c inh2 4.7f c dgnd 4.7f c d2 4.7f r b 10k r fset2 124k r iset2 240k||10k f set compb compa vinreg intv cc clkin run iseta isetb v d sv in v in v out ? sv out ? pgnd gnd pgdfb 4653 f35 pgood d1* *d1: central semi p/n cmmsh1-40l extv cc gnd sns temp + temp ? c out2 22f load r extvcc2 49.9 r track 10k c extvcc2 1f v out ? ?12v up to 3.25a r pgdfb2 95.3k nc sw part number description comments ltm4651 en55022b compliant, 58vin, 24w inverting-output module regulator 3.6v vin 58v, -26.5v vout -0.5v, iout 4a. 15mm x 9mm x 5.01mm bga ltm8045 sepic or inverting module dc/dc converter 2.8v v in 18v, 2.5v v out 15v. i out(dc) 700ma. 6.25mm 11.25mm 4.92mm bga ltm8049 dual, sepic and/or inverting module dc/dc converter 2.6v v in 20v, 2.5v v out 24v. i out(dc) 1a/channel. 9mm 15mm 2.42mm bga ltm8073 60v, 3a step-down module regulator 3.4v v in 60v, 0.8v v out 15v. 6.25mm 9mm 3.32mm bga ltm8064 58v, 6a cvcc step-down module regulator 6v v in 58v, 1.2v v out 36v. 11.9mm x 16mm 4.92mm bga LTM4613 en55022b compliant, 36v, 8a module regulator 5v v in 36v, 3.3v v out 15v. 15mm 15mm 4.32mm lga, and 15mm 15mm 4.92mm bga lt m4653 rev 0

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